Optical links are replacing electrical interconnects in data center infrastructure. Optical links support much higher data rates compared to electrical ones. Optical links also consume a fraction of the power of conventional electrical links. The latest push is to transport at least 100 Gbps on a single wavelength of light. At such rates, the bandwidth of the popular binary NRZ (non-return-to-zero) signaling scheme is too large to be supported by the electrical-to-optical and optical-to-electrical interfaces. Advanced modulation techniques are useful to reduce the required bandwidth. One such technique is pulse-amplitude-modulation with four levels (PAM-4). Two bits are encoded into one of four levels. As a result, the symbol rate (baud rate) will be half of the bit rate and the bandwidth requirement is reduced compared to NRZ signaling. One aspect of this approach is, however, that the signal processing circuits have to be linear. This is a challenge in low-voltage complementary metal-oxide-semiconductor (CMOS) processes. A fine-linewidth CMOS process offers very high speed transistors, but the operating voltage is typically 1 V or less. In order to preserve clearly discernable and equally spaced four levels, the signal processing circuits should exhibit high-linearity and low-noise.
A transimpedance amplifier (TIA) is an element used in converting optical signals to electrical. High-bandwidth linear TIAs are often realized in Indium Phosphide (InP) or Silicon Germanium (SiGe) BiCMOS (Bi-complementary metal-oxide-semiconductor) technologies, where the bipolar transistors offer high speed, low noise, and sustain high voltages. However, the signal processing and logic requirement of a monolithic transceiver integrated circuit (IC) are best realized in CMOS technology. A linear TIA designed in a fine-line CMOS process is likely to face the major technological challenges of signal compression due to limited supply voltage.